Artículos de conferencia

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A baseline restorer for charge-sensitive amplifiers in a 500-nm CMOS process
(IEEE, 2018) Abusleme Hoffman, Ángel Christian; Barraza Altamirano, Renzo Ignacio; Kuleshov, S.
Charge-sensitive amplifiers (CSAs), widely used as front-ends in pulse processors for capacitive detectors, require a feedback network to set the operation point, deal with leakage currents and restore the baseline voltage upon the arrival of signals. Passive feedback networks are simple and reliable solutions that accomplish the task, but cannot modify the operation point in order to accommodate an input with different polarity, and do not offer sufficient flexibility to deal with a wide range of leakage current or input rates. The Krummenacher feedback solves these drawbacks at the cost of a large compensation capacitor, which is required for stability purposes. In this work, a novel configurable feedback network is presented. Based on the same principle as the Krummenacher network, this circuit relies on the design parameters to ensure stability. This work shows analysis, design and test results from a recent implementation in a 500-nm CMOS process.
A Blind Calibration Scheme for Switched-Capacitor Pipeline Analog-to-Digital Converters
(IEEE, 2020) Bozzo Jiménez Juan Andrés; Abusleme Hoffman, Ángel Christian; Martinez, J. S.
A foreground calibration algorithm is proposed to digitally self-calibrate a switched-capacitor (SC), pipelined, analog-to-digital converter (ADC). Static errors resulting from capacitor mismatch, charge transfer loss (from limited amplifier dc gain) and variance in Multiplying DAC (MDAC) voltages are estimated and compensated for. The proposed algorithm reuses the electrical components of the pipeline stages to instantiate Î”Î£ converters in the stages' interfaces. By feeding to those converters self-generated input signals and storing the output stream of codes, the algorithm is able to infer the electrical parameters of the reused elements. The algorithm does not require external stimulus or specialized circuitry to be used as true ground but depends on the stages sub-ADC threshold levels precision, diminishing its performance in circuits where error is dominated by sub-ADC input offset. A number of 10-bit ADC's with a mean uncalibrated Effective Number Of Bits (ENOB) of 6.3 bits where simulated, and a resolution improvement between 2.5 bits, for the best case, and 1 bit for the worst, were observed.
A Digital Memristor Emulator for FPGA-Based Artificial Neural Networks
(IEEE, 2016) Vourkas, Ioannis; Abusleme Hoffman, Ángel Christian; Ntinas, Vasileios; Sirakoulis, Georgios C.; Rubio, Antonio
FPGAs are reconfigurable electronic platforms, well-suited to implement complex artificial neural networks (ANNs). To this end, the compact hardware (HW) implementation of artificial synapses is an important step to obtain human brain-like functionalities at circuit-level. In this context, the memristor has been proposed as the electronic analogue of biological synapses, but the price of commercially available samples still remains high, hence motivating the development of HW emulators. In this work we present the first digital memristor emulator based upon a voltage-controlled threshold-type bipolar memristor model. We validate its functionality in low-cost yet powerful FPGA families. We test its suitability for complex memristive circuits and prove its synaptic properties in a small associative memory via a perceptron ANN.
A Non-Linearity Compensation Technique for Charge-Redistribution SAR ADCs
(IEEE, 2019) Alvarez-Fontecilla, E.; Abusleme Hoffman, Ángel Christian
The linearity of charge-redistribution successive approximation register (SAR) analog-to-digital converters (ADCs) is affected by systematic mismatch in its capacitor array. Fabrication phenomena, such as copper dishing, lead to radial gradients in the array, and the detrimental effect of these gradients cannot be mitigated by the use of common centroid layout techniques. In this work, a technique that uses the foreknowledge of radial gradients in order to shape the linearity of data converters is introduced. By choosing the order in which the capacitors within the physical array are connected during a conversion, it is possible to manipulate the converter linearity, and several integral nonlinearities (INLs) shapes can be obtained. This technique, also applicable for any ADC where the static linearity depends upon the mismatch within an array of regularly-placed circuit elements, has been successfully tested for a 10-bit SAR ADC implemented in a 180-nm CMOS process.
A novel current-based CCD clock driver
(IEEE, 2018) Cancino, B.; Abusleme Hoffman, Ángel Christian
Charge-Coupled Device (CCD) detectors are widely used in astronomy for generating measurable electrical charge from incident photons. The CCD reading process involves a charge transfer stage, in which the charge collected in each pixel is transferred to the output amplifiers. This process is performed by applying a set of clock waveforms to each pixel electrode of the detector. Parameters signals such as voltage excursion, rise/fall times and rise/fall rates, are related directly to the performance of the charge transfer process. Due to the capacitive nature of CCD pixels, the existing clock drivers are not the best suited for the task, because the waveform control is performed by a voltage amplifier. This architecture does not allow to accurately set the rise/fall rate of the voltage signal, since its settling always follows the dynamic response of the amplifier. This paper studies the use of a current-based CCD clock driver implemented through the improved Howland current source (IHCS). This idea takes advantage of the capacitive impedance of CCD pixels, and allows one to accurately set the rise/fall rate of the CCD driving signals, and in consequence, improve the performance of the charge transfer process. A CCD clock driver is designed, built and tested.
BeamCal Instrumentation IC: Design, implementation and test results
(IEEE, 2011) Abusleme Hoffman, Ángel Christian; Dragone, A.; Haller, G.; Wooley, B. A.
The BeamCal detector, one of the calorimeters in the forward region of the International Linear Collider detector, will serve three purposes: ensure hermeticity of the detector for small polar angles, reduce the backscattering from pairs into the detector center, and provide a low-latency signal for beam diagnostics. The BeamCal specifications in terms of noise suppression, signal charge, pulse rate and occupancy pose unique challenges in the front-end and readout electronics design. The Bean - BeamCal Instrumentation IC - is a 32-channel front-end and readout IC that will address the BeamCal instrumentation requirements. By employing switched-capacitor filters and a slow reset-release technique, the Bean will process the signal charge at the International Linear Collider pulse rate. Each channel will have a 10-bit successive approximation analog-to-digital converter and digital memory for readout purposes. The Bean will also feature a fast feedback adder, capable of providing an 8-bit, low-latency output for beam diagnostic purposes. This work presents the design and characterization of the Bean prototype, a 3-channel IC that proves the principle of operation described.
Digital assistance for energy reduction in ADCs using a simple signal prediction algorithm
(IEEE, 2014) Avila, Diego; Alvarez Fontecilla, Enrique; Abusleme Hoffman, Ángel Christian
With the adoption of new technology nodes q for analog circuits, different digital techniques have been designed to enhance their performance. Among the existing techniques, a promising approach is to adapt the circuit operation dynamically considering the application characteristics. In the field of analog-to-digital converters (ADCs), typically this approach is carried out by taking advantage of application-dependent signal properties, hence their use is limited. In this work, a digital assistance technique for power reduction in ADCs is presented. By defining a reduced valid range for the next sample based upon the maximum possible change of the input signal between samples, the proposed algorithm reduces the mean energy consumption per conversion in a variety of ADC architectures, regardless of the application.
Exploring the voltage divider approach for accurate memristor state tuning
(IEEE, 2017) Vourkas, Ioannis; Gómez Luna, Jorge Antonio; Abusleme Hoffman, Ángel Christian; Vasileiadis, Nikolaos; Sirakoulis, Georgios C.; Rubio, Antonio
The maximum exploitation of the favorable properties and the analog nature of memristor technology in future nonvolatile resistive memories, requires accurate multi-level programming. In this direction, we explore the voltage divider (VD) approach for highly controllable multi-state SET memristor tuning. We present the theoretical basis of operation, the main advantages and weaknesses. We finally propose an improved closed-loop VD SET scheme to tackle the variability effect and achieve <;1% tuning precision, on average 3x faster than another accurate tuning algorithm of the recent literature.
Fully-differential offset-cancelling circuit with configurable output common-mode voltage
(IEEE, 2013) Álvarez Fontecilla, Enrique; Avila, D.; Campillo Mecklenburg, Hernán; Abusleme Hoffman, Ángel Christian
For certain applications, the offset voltage of the amplifiers represents a problem that must be addressed, since it may affect the transfer characteristics of the system. Offset memorization techniques allow to partially cancel the offset voltage either at the input or at the output of an amplifier, but their effectiveness is highly dependent on the amplifier gain. For this reason, these techniques do not result in a complete offset cancellation when used with low-gain amplifiers. In this work, a fully-differential offset-cancelling circuit based on offset memorization techniques is introduced along with its analysis and simulation results. Among the features of the proposed circuit are a configurable output common-mode voltage and a complete offset cancellation even when used with low-gain amplifiers.
Fuzzy control for the Kadet senior radiocontrolled airplane
(IEEE, 2001) Abusleme Hoffman, Ángel Christian; Cipriano, Aldo; Guarini Hermann, Marcelo Walter
Three control strategies for the longitudinal dynamics of a Kadet Senior radiocontrolled airplane are analyzed and compared through simulation of a global nonlinear mathematical model. The first strategy uses a PID controller for the speed and two PID cascade controllers for the climb rate and altitude. The second strategy is a control system based on fuzzy logic. The third strategy consists of a hybrid system with a PID controller for the climb rate and fuzzy controllers for the speed and altitude.
Improved performance of a battery powered electric car, using photovoltaic cells
(IEEE, 2003) Abusleme Hoffman, Ángel Christian; Dixon Rojas, Juan; Soto, Daniel
One of the major problems for the massive applicability of electric vehicles (EVs) is the scarce capacity of conventional electrical energy storage systems. Although this constraint has been overcome in many cases using advanced technologies such as fuel cells and high-capacity batteries, it is still difficult to develop an economically viable and socially acceptable EV for massive use. In this context, solar energy is not a practical solution for satisfying this lack of energy. However, if a particular situation is considered, in which a small-sized, high-efficiency EV operates at low duty cycles in a sunny, predictable environment, solar power can become a solution for reducing transport costs. This paper deals with the reach of this approach.
Resistive Switching Behavior seen from the Energy Point of View
(IEEE, 2018) Gomez Mir, Jorge Tomás; Abusleme Hoffman, Ángel Christian; Vourkas, I.; Rubio, A.
The technology of Resistive Switching (RS) devices (memristors) is continuously maturing on its way towards viable commercial establishment. So far, the change of resistance has been identified as a function of the applied pulse characteristics, such as amplitude and duration. However, parameter variability holds back any universal approach based on these two magnitudes, making also difficult even the qualitative comparison between different RS material compounds. On the contrary, there is a relevant magnitude which is much less affected by device variability; the energy. In this direction, we doubt anyone so far has ever wondered "what is the quantitative effect of the injected energy on the device state?" Interestingly, a first step was made recently towards the definition of performance parameters for this emerging device technology, using as fundamental parameter the energy. In this work, we further elaborate on such ideas, proving experimentally that the "resistance change per energy unit" (dRidE) can be considered a significant magnitude in analog operation of bipolar memristors, being a key performance parameter worth of timely disclosure.
Towards memristive crossbar-based neuromorphic HW accelerators for signal processing
(IEEE, 2017) Vourkas, I.; Abusleme Hoffman, Ángel Christian; Vasileiadis, N.; Sirakoulis, G. C.; Papamarkos, N.
Research progress in neuromorphic hardware, capable of biological perception and cognitive information processing, is leading the way towards a revolution in computing technology. Current research efforts have focused mainly on resistive switching devices, the electronic analog of synapses in artificial neural networks (ANNs), and the crossbar nanoarchitecture, for its huge connectivity and maximum integration density. In this context, this work presents the design and simulation of a memristive crossbar-based ANN for text recognition tasks, implementing a novel computing algorithm. In such case study, important issues during the application mapping process are identified and properly addressed at device and circuit level. The computing capabilities of the proposed system are highlighted through SPICE-level circuit simulations, which show excellent agreement with theoretical simulation results.
Voltage Divider for Self-Limited Analog State Programing of Memristors
(IEEE, 2020) Vourkas, Ioannis; Gómez, Jorge; Abusleme Hoffman, Ángel Christian; Sirakoulis, Georgios Ch.; Rubio, Antonio
Resistive switching devices âˆ’memristors âˆ’present a tunable, incremental switching behavior. Tuning their state accurately, repeatedly and in a wide range, makes memristors well-suited for multi-level (ML) resistive memory cells and analog computing applications. In this brief, the tuning approach based on a memristor-resistor voltage divider (VD) is validated here experimentally using commercial memristors from Knowm Inc. and a custom circuit. Rapid and controllable multi-state SET tuning is shown with an appreciable range of different resistance values obtained as a function of the amplitude of the applied voltage pulse. The efficiency of the VD is finally compared against an adaptive pulse-based tuning protocol, in terms of circuit overhead, tuning precision, tuning time, and energy consumption, qualifying as a simple hardware solution for fast, reliable, and energy-efficient ML resistance tuning.

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