A Blind Calibration Scheme for Switched-Capacitor Pipeline Analog-to-Digital Converters

No Thumbnail Available
Journal Title
Journal ISSN
Volume Title
A foreground calibration algorithm is proposed to digitally self-calibrate a switched-capacitor (SC), pipelined, analog-to-digital converter (ADC). Static errors resulting from capacitor mismatch, charge transfer loss (from limited amplifier dc gain) and variance in Multiplying DAC (MDAC) voltages are estimated and compensated for. The proposed algorithm reuses the electrical components of the pipeline stages to instantiate ΔΣ converters in the stages' interfaces. By feeding to those converters self-generated input signals and storing the output stream of codes, the algorithm is able to infer the electrical parameters of the reused elements. The algorithm does not require external stimulus or specialized circuitry to be used as true ground but depends on the stages sub-ADC threshold levels precision, diminishing its performance in circuits where error is dominated by sub-ADC input offset. A number of 10-bit ADC's with a mean uncalibrated Effective Number Of Bits (ENOB) of 6.3 bits where simulated, and a resolution improvement between 2.5 bits, for the best case, and 1 bit for the worst, were observed.
Capacitors, Pipelines, Calibration, Computational modeling, Uncertainty, Charge transfer, Clocks